The semiconductor industry has constantly pursued higher device densities with lower costs. Technological advances in semiconductor device, or integrated circuit (IC), materials, designs and manufacturing processes have produced progressively smaller circuits. In the course of this IC evolution, functional density (for example, the number of interconnected devices per chip area) has generally increased while geometry sizes have decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs
The general manufacturing scheme of an IC includes two parts, front end of line (FEOL) processing and back end of line (BEOL) processing. Generally, BEOL contains passive, linear devices made from metals and insulators, such as signal and power wires, transmission lines, metal resistors, metal-insulator-metal (MIM) capacitors, inductors, and fuses. BEOL may include devices being wired together with a patterned multilevel metallization process.
This scaling down process has increased the complexity of processing and manufacturing ICs. As device density increases and device scale decreases, short circuits or cross talk may occur during BEOL processing in ICs, resulting in the decrease of yield.
Therefore, conventional semiconductor device fabrication and processing techniques have not been entirely satisfactory.